71V2556S, 71V2556SA 128K x 36 3.3V Synchronous ZBT™ SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
●说明：
■IDT71V256是一款3.3V高速4718592位（4.5兆位）同步SRAM。它的设计目的是在读取和写入或写入和读取之间切换总线时消除死总线周期。因此，他们被命名为ZBT™ , 或零总线转弯
■地址和控制信号在一个时钟周期内被施加到SRAM，两个周期后发生相关的数据周期，无论是读取还是写入。
■IDT71V256包含数据I/O、地址和控制信号寄存器。输出启用是唯一的异步信号，可用于在任何给定时间禁用输出。
■时钟启用（CEN）引脚允许IDT71V2556的操作在必要时暂停。当（CEN）为高时，所有同步输入被忽略，并且内部设备寄存器将保持其先前的值。
■有三个芯片使能引脚（CE1、CE2、CE2），允许用户在需要时取消选择设备。当ADV/LD为低电平时，如果这三者中的任何一个未被断言，则不能启动新的存储器操作。但是，任何挂起的数据传输（读取或写入）都将完成。在芯片被取消选择或写入被启动后的两个周期，数据总线将处于三态。
■IDT71V256具有一个片上突发计数器。在突发模式中，IDT71V256可以为呈现给SRAM的单个地址提供四个周期的数据。突发序列的顺序由LBO输入引脚定义。LBO引脚在线性突发序列和交错突发序列之间进行选择。ADV/LD信号用于加载新的外部地址（ADV/LD=LOW）或增加内部突发计数器（ADV/LD=HIGH）。
■IDT71V256 SRAM采用高性能CMOS工艺，封装在JEDEC标准14mm x 20mm薄塑料四片扁平封装（TQFP）和119球栅阵列（BGA）中。
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71V2556S、71V2556SA 128K X 36 3.3V同步ZBT™SRAM 2.5V I/O，脉冲串计数器流水线输出 |
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71V2556S、71V2556SA、71V2556S100PFG、71V2556S100PFG8、71V2556S100PFGI、71V2556S100PFGI8、71V2556S133PFG、71V2556S133PFG8、71V2556S133PFGI、71V2556S133PFGI8、71V2556S150PFG、71V2556S150PFG8、71V2556S150PFGI、71V2556S150PFGI8、71V2556S166PFG、71V2556S166PFG8、71V2556S166PFGI、71V2556S166PFGI8、71V2556SA100BG、71V2556SA100BG8、71V2556SA100BGG、71V2556SA100BGG8、71V2556SA100BGGI、71V2556SA100BGGI8、71V2556SA100BGI、71V2556SA100BGI8、71V2556SA133BG、71V2556SA133BG8、71V2556SA133BGI、71V2556SA133BGI8、71V2556SA166BG、71V2556SA166BG8、IDT71V2556、71V2556 |
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同步ZBT™SRAM、128Kx36流水线ZBT SRAM、3.3V高速4718592位（4.5兆位）同步SRAM、SRAM |
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DATA SHEET,数据手册,数据表 |
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详见资料 |
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BGA;TQFP;PBGA;BG119;BGG119;PKG100 |
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中文 英文 中英文 日文 |
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Aug.20.20 |
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1 MB |
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