New Die Package Extends 3D TLC e.MMC Endurance to MLC/SLC Levels of ATP E750Pi/Pc, E650Si/Sc Series e.MMC

2022-02-17 ATP ELECTRONICS

Taipei, Taiwan (February) – ATP Electronics, the global leader in specialized storage and memory solutions, has introduced its latest line of e.MMC devices built on 3D triple level cell (TLC) NAND. Using a new die package, the E750Pi/Pc and E650Si/Sc Series offer long-life performance, optimized power consumption and customizable configuration options.


ATP ELECTRONICS's new E750Pi/Pc Series e.MMC offerings are built with 3D TLC NAND flash but are configured as pseudo SLC (pSLC) to offer endurance on par with SLC NAND, while E650Si/Sc Series in native TLC has near-MLC endurance.


The E750Pi and E650Si Series are industrial temperature-operable (-40°C to 85°C), making them ideal for deployment in scenarios with extreme thermal challenges and harsh environments, while E750Pc and E650Sc support -25°C to 85°C operating temperatures for applications with non-critical thermal requirements.


“Industrial and embedded applications are becoming more varied, requiring storage devices to be more flexible with a wide array of specifications and options. The ATP e.MMC’s small footprint makes it a suitable, cost-effective solution for space-constrained environments. As a soldered-down solution, it is shock/vibration proof, so it has become a preferred storage medium for extremely rugged operations.” said Chris Lien, Head of the Embedded Business Unit at ATP. “As customers become more discerning in choosing data storage solutions to meet specific needs, ATP’s customization capabilities allow us to tailor-fit configurations to deliver better power efficiency, space-saving packages, and ball variations.”

 

Huge Features in a Tiny Footprint. Consuming low power during Sleep Mode, the E750Pi/Pc and E650Si/Sc Series e.MMC deliver huge power savings. The new e.MMC offerings comply with JEDEC e.MMC v5.1 standard (JESD84-B51), supporting high-speed 400 (HS400) DDR mode for a bandwidth of up to 400 MB/s.


The E650Si/Sc Series in native TLC offer capacities from 32 to 64 GB for use in mass storage applications, while the E750Pi/Pc in pSLC mode are available in capacities from 10 GB to 21 GB, which cuts down the TLC capacity but improves performance, reliability, and endurance.


Data Integrity Features

The ATP E750Pi/Pc and E650Si/Sc Series e.MMC feature the following technologies to ensure high levels of data integrity:

●AutoRefresh Technology improves the data integrity of read-only areas by monitoring the error bit level and read counts in every read operation.

●Dynamic Data Refresh Technology reduces the risks of read disturb and sustains data integrity in seldom-accessed areas.

●SRAM Soft Error Detector and Recovery mechanism maximizes data integrity by monitoring soft errors, which cannot be detected nor solved by ECC engines and can therefore significantly jeopardize data accuracy.

●Low-Density Parity-Check Error Correcting Code (LDPC ECC) provides powerful error correction to significantly improve data transfer reliability.

 

Customizable Configurations  

Apart from the standard e.MMC size of 11.5 x 13 mm, customers may request a customized package size, such as the 9 x 10 mm option, for up to 40% space savings. ATP also offers value-added services to further optimize and tune power consumption. The E750Pi/Pc and E650Si/Sc Series e.MMC come in the standard 153-ball grid array (BGA) but depending on project, other ball variations such as the 100-ball option, may be requested. Other customizable configurations include firmware, testing, laser markings, and other specific features to meet their investment and application requirements.

 

Specifications


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本文由星晴123转载自ATP ELECTRONICS,原文标题为:New Die Package Extends 3D TLC e.MMC Endurance to MLC/SLC Levels of ATP E750Pi/Pc, E650Si/Sc Series e.MMC,本站所有转载文章系出于传递更多信息之目的,且明确注明来源,不希望被转载的媒体或个人可与我们联系,我们将立即进行删除处理。

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