Closing the Performance Gap Between DRAM and AI Processors

时间： 2023-11-03 来源：RENESAS Blogs

技术问答

选型帮助

研发客服

商务客服

As the workhorse of semiconductor memory, DRAM holds a unique place in the industry thanks to its large storage capacity and ability to feed data and program code to the host processor quickly.

Lately, this unsung hero of the circuit board has been taking a backseat to its logic counterparts, as a wave of high-performance FPGAs, CPUs, GPUs, TPUs, and custom accelerator ASICs emerges to meet the massive data processing demands of predictive and generative AI applications. The sheer compute density of these rapidly emerging AI accelerators is shattering even the most ambitious expectations, and the number of processor cores inside data center servers continues to balloon.

However, such explosive growth has had consequences, given that advanced logic scaling continues to outpace DRAM scaling. This gap contributes to a widening performance mismatch between the two that threatens to compromise server performance by forcing high-speed (and costly) processors to waste compute cycles while waiting for main memory to catch up.

A New Approach to DRAM Interface Design

Of course, such imbalances are nothing new. The very nature of the classic Von Neumann model specifies the decoupling of the processor and memory, which creates a chokepoint that prevents designers from optimizing every compute cycle. With the industry’s design and manufacturing investment roadmaps more or less wedded to this architectural paradigm for the foreseeable future, RENESAS needs a new approach to bring processors and memory into closer alignment.

Figure 1 - Von Neumann Architecture

Indeed, DRAM designers are rushing to close the rift, most notably with the introduction of high-speed, high-capacity, third-generation DDR5 DRAM. But more must be done to mesh computing and memory. That was the motivation that drove Renesas to recently launch a registered clock driver (RCD) and client clock driver (CKD) for third-generation DDR5 DRAM servers and client systems across RENESAS entire portfolio of memory interfaces for dual inline memory modules (DIMMs), motherboards and embedded applications.

The new DDR5 RCD and DDR5 CKD ICs enable next-generation DIMMs with speeds of up to 6400 and 7200 mega transfers per second (MT/s), respectively, an increase from today’s 5600 MT/s transfer speeds. Renesas’ Gen 3 DDR5 RCD is designed for registered DIMMs (RDIMMs). The CKD is the first in the industry to interface with small-outline DIMMs (SODIMMs), unbuffered DIMMs (UDIMMs), high-performance gaming DIMMs, and memory-down applications for client platforms.

Figure 2 – DDR5 Server DIMM

Together, these new drivers enable a hierarchy of memories operating at different performance, power, and capacity levels. Their adoption is expected to drive the growth of so-called “chipsets,” an emerging form of heterogeneous computing that converges components with different functions, process nodes, and electrical characteristics. Heterogeneous computing is also driving research into new approaches to memory and logic within the device and module, inside the server, and across the entire server rack.

The Importance of Ecosystem Collaboration

RENESAS did not achieve this breakthrough in a vacuum. Working closely with the JEDEC standards body, Renesas is facilitating an ecosystem of development partners and serves as the glue that holds together DRAM and DIMM makers, CPU, GPU, and other logic providers, server designers – even hyperscale computing operators like Amazon, Google, and Microsoft. In addition to setting a shared roadmap and key performance indicators, the collective ensures design verification and interoperability testing at the device, module, and system level – and across all relevant software applications.

The imperative for close collaboration also led us to join the Compute Express Link™ (CXL™) Consortium. The consortium aims to develop open-source standards and technical specifications for data center interconnect. This includes a high-speed memory fabric that achieves performance parity with various forms of computing system architectures.

Ultimately, RENESAS' goal at Renesas is to empower device, module, and system architects to break conventional design constraints. Together, RENESAS can unleash the potential of a co-optimized compute-memory architecture and better meet the needs of increasingly sophisticated – and compute-intensive – AI applications.

发送到邮箱 |
+1 赞 0
收藏
评论 0
| 转发至：

本文由翊翊所思转载自RENESAS Blogs，原文标题为:Closing the Performance Gap Between DRAM and AI Processors，本站所有转载文章系出于传递更多信息之目的，且明确注明来源，不希望被转载的媒体或个人可与我们联系，我们将立即进行删除处理。

全部评论（0）

暂无评论

What is Driving DDR5? ＆ What does Renesas offer for DDR5?

Renesas‘ family of DDR5 and I³C expander ICs enables the next generation of server and client DIMM as well as server and client motherboard solutions to efficiently scale to superior performance, density and reliability while reducing overall system power.

设计经验发布时间 : 2021-11-03

A Registering Clock Driver Used on DDR5 RDIMMs and LRDIMMs——Renesas RCD 5RCD0148HC2

The Renesas 5RCD0148HC2 (RCD) is a registering clock driver used on DDR5 RDIMMs and LRDIMMs. Its primary function is to buffer the Command Address (CA) bus, chip selects, and clock between the host controller and the DRAMs. It also creates a BCOM bus to control the data buffers for LRDIMMs.

新产品发布时间 : 2021-11-05

瑞萨为高性能DDR5 DIMM开发提供一站式解决方案，给予卓越性能、密度和可靠性并降低整体系统功耗

与前几代DDR内存接口产品一样，瑞萨的器件处于市场领先地位。瑞萨拥有一个完整的IC系列来开发高性能的DDR5 DIMM，包括-RDIMM、LRDIMM、NVDIMM、UDIMM、SODIMM、游戏DIMM，以及用于服务器和客户端内存下降应用的内存接口产品。

厂牌及品类发布时间 : 2021-10-31

Renesas Introduces Industry’s First Client Clock Driver and Gen 3 RCD to Enable Demanding DDR5 Client and Server DIMMs

The DDR5 RCD and DDR5 CKD ICs enable the next generation of DIMMs with speeds of up to 6400 and 7200 mega transfers per second (MT/s), respectively, an increase from today’s 5600 MT/s transfer speeds. Renesas’ Gen 3 DDR5 RCD is designed for registered DIMMs (RDIMMs).

新产品发布时间 : 2023-06-30