C-V Curve Matters for Quiet Power Electronics

Key Takeaways:

·Abrupt change of Cgd causes uncontrolled high dV/dt during switching transients results in oscillations and generates EMI.

·Abrupt change of Cgd with Vds has an adverse effect on EMI/EMC. Device with a smoother C-V curve performs better.

·Abrupt change of capacitive ratio Cgd/Cgs with Vds also adversely impacts EMI/EMC, smoother is better.

A paper published by ST Microelectronics at PCIM Europe 2014 discussed how the intrinsic capacitances of power MOSFETs may affect the electromagnetic interferences (EMI) and electromagnetic compatibility (EMC) of power electronics. In addition to the factors usually mentioned such as "component's placing on printed circuit boards" or "parasitic tanks created by traces and dielectric insulation", the parasitic parameters of power MOSFETs, particularly how the capacitances change with drain-to-source voltage Vds, could also affect the performance of EMI/EMC.

The authors compared two devices with similar parameters except for the characteristics of capacitance versus voltage (C-V) curves. One of the devices has a more linear, gradual change of capacitance with Vds, the other one has a highly non-linear, abrupt change of capacitance with Vds. And they found that the device with an abrupt drop of capacitance resulted in a high-frequency oscillation of Vds and Vgs, and generated significantly higher EMI exceeding the regulation required maximum value. This is because during the charging and discharging of MOSFET reverse transfer capacitance (Crss, or Miller capacitance, Cgd), a sudden change of capacitance would result in very high dV/dt, which coupling with other parasitics, would then cause oscillations.

Besides the shape of CV curves, the authors also found that the shape of capacitive ratio (R) between Cgd and Cgs (R=Cgd/Cgs or Crss/Ciss) with Vds also has an impact on the performance of EMI/EMC. Similar to C-V curves, a smoother R-V curve performs better on EMI/EMC.

Similar observations were also found in another paper published at IEEE ICSICT 2016 by authors from Peking University, Fudan University, and Suzhou Oriental Semiconductor. The abrupt change Cgd in silicon super-junction MOSFET (Si SJ MOSFET) is originated from the merged depletion layers from adjacent p-type pillars which suddenly reduce the capacitance to a very low value. This abrupt change of Cgd would result in an abrupt change of voltage drop on the series gate resistor during the charging and discharging of Miller capacitance, cause oscillations of gate voltage and drain voltage, and generate EMI. With all other factors kept the same, devices with smoother C-V curve could provide more EMI margin compared to devices with abrupt Cgd change and thus enable higher switching frequency. Newer generations of Si SJ MOSFETs usually exhibit a more abrupt change in Cgd because of reduced cell pitch, this may be one of the reasons why it often requires more efforts to deal with the EMI/EMC issues when using newer generations of Si SJ MOSFETs.