【应用】SI569可编程VCXO完美支持200/400G高速相干光模块时钟链路设计
随着近年来光通信及互联网络的高速发展,互联网业务容量以超摩尔定律的速率发展,直接导致了电信骨干网的流量每年正以接近80%的速度飞速增长,用于实现互联网的光传输、数据中心设备的光模块速率从25G、40G到目前已经大规模应用的100G光模块,高速光模块获得迅速增长,目前在研的高速模块已经突破到了200G/400G甚至600G速率。
高速光模块的发展取决于DSP和高速ADC/DAC等技术的发展,目前主流DSP厂家如NEL、INPHI等公司推出了基于200G/400G速率的高速光模块DSP处理器。
在高速光模块设计中,时钟链路设计一直是高速模块中的设计重点。高速DSP一般都会需要高速的时钟源(晶振/PLL),高速的ADC和DAC(可能内置于DSP中)也需要高速率时钟,为了保证信号的实时处理,200G/400G光模块对外围时钟的jitter(相噪)和稳定度有较高的要求。
200G/400相干光模块是用于线路侧的高速光模块,时钟设计通常包括三个时钟链路,分别是RX端时钟、TX端发端时钟和DSP内部/外部ADC高速采样时钟。DSP与ADC/DAC之间要实现频率、相位动态调整,设计时会考虑在DSP和ADC/DAC之间搭建一个自行设计的锁相环,该锁相环会由FPGA、外置PD、LPF加VCXO组成,由DSP动态控制,工作时实现频率动态调整输出给后端的ADC/DAC。出于设计需要,一般要求该VCXO的RMS jitter指标要好,同时要求稳定度至少在50ppm以内,同时由于要追踪频率变化较宽的参考源时钟,要求VCXO的APR必须较大。
SILICON LABS的高性能可编程VCXO SI569正是满足这种设计的最佳晶振,SI569的RMS jitter在115fs左右,最大APR可以达到215ppm/V(在3.3V条件下),同时SI 569支持I2C可编程输出,可以在0.2~2200MHz之间实现连续可调,完美支持200G/400G高速相干光模块时钟链路设计。
图1 基于Silicon Labs高性能可编程VCXO SI569的光模块时钟链路设计
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品类:Switch Hall Effect Magnetic Position Sensor
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