【经验】R-Car H3 bsp如何实现PCIE endpoint模式？
PCIE(peripheral component interconnect express)是一种高速串行计算机扩展总线标准，属于高速串行点对点双通道高带宽传输，所连接的设备分配独享通道带宽，不共享总线带宽，支持主动电源管理，错误报告，端对端的可靠性传输，热插拔以及服务质量(QOS)等功能。是当前比较流行的一种高速总线接口。
R-Car系列作为瑞萨在高端汽车电子应用市场的主力产品，除了最低端的R-Car D3和专用于ADAS的R-Car V3M，其他型号都是集成了PCIE2.0接口的，该接口可以支持root port和endpoint也就是主从两种模式的，最近有用户在使用两颗R-Car H3做PCIE通讯测试时发现无法配置成endpoint模式，经过测试及追查源代码发现，bsp中PCIE驱动没有对endpoint模式做支持，因此需要自行修改相应的驱动代码。
修改方法介绍如下，添加patch或者修改源码后，重新编译内核即可。由于测试条件所限，笔者未能验证改方法实际效果，仅限理论上可行，因此仅供参考。
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index b022ac5678f7..69b1c778dad4 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -61,6 +61,13 @@ config PCIE_RCAR_HOST
help
Say Y here if you want PCIe controller support on R-Car SoCs in host mode.
+config PCIE_RCAR_EP
+ bool "RENESAS R-Car PCIe endpoint controller"
+ depends on ARCH_RENESAS || COMPILE_TEST
+ depends on PCI_ENDPOINT
+ help
+ Say Y here if you want PCIe controller support on R-Car SoCs in endpoint mode.
+
config PCI_HOST_COMMON
bool
select PCI_ECAM
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 69ba1dbf837b..61505b1fc66a 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_PCI_AARDVARK) += pci-aardvark.o
obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
obj-$(CONFIG_PCIE_RCAR_HOST) += pcie-rcar.o pcie-rcar-host.o
+obj-$(CONFIG_PCIE_RCAR_EP) += pcie-rcar.o pcie-rcar-ep.o
obj-$(CONFIG_PCI_HOST_COMMON) += pci-host-common.o
obj-$(CONFIG_PCI_HOST_GENERIC) += pci-host-generic.o
obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o
diff --git a/drivers/pci/host/pcie-rcar-ep.c b/drivers/pci/host/pcie-rcar-ep.c
new file mode 100644
index 000000000000..40cd2aad8c3c
--- /dev/null
+++ b/drivers/pci/host/pcie-rcar-ep.c
@@ -0,0 +1,497 @@
+/*
+ * PCIe endpoint driver for Renesas R-Car SoCs
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_pci.h>
+#include <linux/of_platform.h>
+#include <linux/pci.h>
+#include <linux/pci-epc.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+
+#include "pcie-rcar.h"
+
+#define MAX_NR_INBOUND_MAPS 6
+#define MAX_NR_OUTBOUND_MAPS 4
+
+/* Structure representing the PCIe interface */
+struct rcar_pcie {
+ phys_addr_t *ob_addr;
+ struct pci_epc_mem_window *ob_window;
+ struct pci_epc *epc;
+ struct device *dev;
+ void __iomem *base;
+ u8 max_functions;
+ unsigned int bar_to_atu[MAX_NR_INBOUND_MAPS];
+ unsigned long *ib_window_map;
+ u32 num_ib_windows;
+ u32 num_ob_windows;
+};
+
+static void rcar_pcie_ep_hw_init(struct rcar_pcie *pcie)
+{
+ u32 val;
+
+ rcar_pci_write_reg(pcie->base, 0, PCIETCTLR);
+
+ /* Set endpoint mode */
+ rcar_pci_write_reg(pcie->base, 0, PCIEMSR);
+
+ /* Initialize default capabilities. */
+ rcar_rmw32(pcie->base, REXPCAP(0), 0xff, PCI_CAP_ID_EXP);
+ rcar_rmw32(pcie->base, REXPCAP(PCI_EXP_FLAGS), PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ENDPOINT << 4);
+ rcar_rmw32(pcie->base, RCONF(PCI_HEADER_TYPE), 0x7f, PCI_HEADER_TYPE_NORMAL);
+
+ /* Write out the physical slot number = 0 */
+ rcar_rmw32(pcie->base, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0);
+
+ val = rcar_pci_read_reg(pcie->base, EXPCAP(1));
+ /* device supports fixed 128 bytes MPSS */
+ val &= ~GENMASK(2, 0);
+ /* L1 to L0 transition latency no time limit */
+ val |= GENMASK(11, 9);
+ /* L0s to L0 transistion no time limit */
+ val |= GENMASK(8, 6);
+ rcar_pci_write_reg(pcie->base, val, EXPCAP(1));
+
+ val = rcar_pci_read_reg(pcie->base, EXPCAP(2));
+ /* read requests size 128 bytes */
+ val &= ~GENMASK(14, 12);
+ /* payload size 128 bytes */
+ val &= ~GENMASK(7, 5);
+ /* disable relaxed ordering transaction */
+ val &= ~BIT(4);
+ rcar_pci_write_reg(pcie->base, val, EXPCAP(2));
+
+ val = rcar_pci_read_reg(pcie->base, EXPCAP(4));
+ /* disable ASPM control */
+ val &= ~GENMASK(1, 0);
+ rcar_pci_write_reg(pcie->base, val, EXPCAP(4));
+
+ /* Set target link speed to 5.0 GT/s */
+ rcar_rmw32(pcie->base, EXPCAP(12), PCI_EXP_LNKSTA_CLS, PCI_EXP_LNKSTA_CLS_5_0GB);
+
+ /* Set the completion timer timeout to the maximum 50ms. */
+ rcar_rmw32(pcie->base, TLCTLR + 1, 0x3f, 50);
+
+ /* Terminate list of capabilities (Next Capability Offset=0) */
+ rcar_rmw32(pcie->base, RVCCAP(0), 0xfff00000, 0);
+
+ /* flush modifications */
+ wmb();
+}
+
+static int rcar_pcie_parse_outbound_ranges(struct rcar_pcie *pcie, struct platform_device *pdev)
+{
+ char outbound_name[10];
+ struct resource *res;
+ unsigned int i = 0;
+
+ pcie->num_ob_windows = 0;
+ for (i = 0; i < MAX_NR_OUTBOUND_MAPS; i++) {
+ sprintf(outbound_name, "memory%u", i);
+ res = platform_get_resource_byname(pdev,
+ IORESOURCE_MEM,
+ outbound_name);
+ if (!res) {
+ dev_err(pcie->dev, "missing outbound window %u\n", i);
+ return -EINVAL;
+ }
+ if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res),
+ outbound_name)) {
+ dev_err(pcie->dev, "Cannot request memory region %s.\n", outbound_name);
+ return -EIO;
+ }
+
+ pcie->ob_window[i].phys_base = res->start;
+ pcie->ob_window[i].size = resource_size(res);
+ /* controller doesn't support multiple allocation
+ * from same window, so set page_size to window size
+ */
+ pcie->ob_window[i].page_size = resource_size(res);
+ }
+ pcie->num_ob_windows = i;
+
+ return 0;
+}
+
+static int rcar_pcie_ep_get_pdata(struct rcar_pcie *pcie, struct platform_device *pdev)
+{
+ struct pci_epc_mem_window *window;
+ struct device *dev = pcie->dev;
+ struct resource res;
+ int err;
+
+ err = of_address_to_resource(dev->of_node, 0, &res);
+ if (err)
+ return err;
+ pcie->base = devm_ioremap_resource(dev, &res);
+ if (IS_ERR(pcie->base))
+ return PTR_ERR(pcie->base);
+
+ pcie->ob_window = devm_kcalloc(dev, MAX_NR_OUTBOUND_MAPS, sizeof(*window), GFP_KERNEL);
+ if (!pcie->ob_window)
+ return -ENOMEM;
+
+ rcar_pcie_parse_outbound_ranges(pcie, pdev);
+
+ err = of_property_read_u8(dev->of_node, "max-functions", &pcie->max_functions);
+ if (err < 0)
+ pcie->max_functions = 1;
+
+ return 0;
+}
+
+static int rcar_pcie_ep_write_header(struct pci_epc *epc, u8 fn, struct pci_epf_header *hdr)
+{
+ struct rcar_pcie *ep = epc_get_drvdata(epc);
+ u32 val;
+
+ if (!fn)
+ val = hdr->vendorid;
+ else
+ val = rcar_pci_read_reg(ep->base, IDSETR0);
+ val |= hdr->deviceid << DEVICE_ID_SHFIT;
+ rcar_pci_write_reg(ep->base, val, IDSETR0);
+
+ val = hdr->revid;
+ val |= hdr->progif_code << 8;
+ val |= hdr->subclass_code << 16;
+ val |= hdr->baseclass_code << 24;
+ rcar_pci_write_reg(ep->base, val, IDSETR1);
+
+ if (!fn)
+ val = hdr->subsys_vendor_id;
+ else
+ val = rcar_pci_read_reg(ep->base, SUBIDSETR);
+ val |= hdr->subsys_id << 16;
+ rcar_pci_write_reg(ep->base, val, SUBIDSETR);
+
+ if (hdr->interrupt_pin > PCI_INTERRUPT_INTA)
+ return -EINVAL;
+ val = rcar_pci_read_reg(ep->base, PCICONF(15));
+ val |= (hdr->interrupt_pin << 8);
+ rcar_pci_write_reg(ep->base, val, PCICONF(15));
+
+ return 0;
+}
+
+static int rcar_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, struct pci_epf_bar *epf_bar)
+{
+ struct rcar_pcie *ep = epc_get_drvdata(epc);
+ dma_addr_t cpu_addr = epf_bar->phys_addr;
+ int flags = epf_bar->flags | LAR_ENABLE | LAM_64BIT;
+ enum pci_barno bar = epf_bar->barno;
+ u64 size = 1ULL << fls64(epf_bar->size - 1);
+ u32 mask;
+ int idx;
+ int err;
+
+ idx = find_first_zero_bit(ep->ib_window_map, ep->num_ib_windows);
+ if (idx >= ep->num_ib_windows) {
+ dev_err(ep->dev, "no free inbound window\n");
+ return -EINVAL;
+ }
+
+ if ((flags & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO)
+ flags |= IO_SPACE;
+
+ ep->bar_to_atu[bar] = idx;
+ /* use 64 bit bars */
+ set_bit(idx, ep->ib_window_map);
+ set_bit(idx + 1, ep->ib_window_map);
+
+ if (cpu_addr > 0) {
+ unsigned long nr_zeros = __ffs64(cpu_addr);
+ u64 alignment = 1ULL << nr_zeros;
+
+ size = min(size, alignment);
+ } else {
+ size = size;
+ }
+
+ size = min(size, 1ULL << 32);
+
+ mask = roundup_pow_of_two(size) - 1;
+ mask &= ~0xf;
+
+ rcar_pcie_set_inbound(ep->base, cpu_addr, 0x0, mask | flags, idx, false);
+
+ err = rcar_pcie_wait_for_phyrdy(ep->base);
+ if (err) {
+ dev_err(ep->dev, "phy not ready\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static void rcar_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn, struct pci_epf_bar *epf_bar)
+{
+ struct rcar_pcie *ep = epc_get_drvdata(epc);
+ enum pci_barno bar = epf_bar->barno;
+ u32 atu_index = ep->bar_to_atu[bar];
+
+ rcar_pcie_set_inbound(ep->base, 0x0, 0x0, 0x0, bar, false);
+
+ clear_bit(atu_index, ep->ib_window_map);
+ clear_bit(atu_index + 1, ep->ib_window_map);
+}
+
+static int rcar_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, phys_addr_t addr, int window,
u64 pci_addr, size_t size)
+{
+ struct rcar_pcie *ep = epc_get_drvdata(epc);
+ struct resource res;
+ int err;
+
+ /* check if we have a link. */
+ err = rcar_pcie_wait_for_dl(ep->base);
+ if (err) {
+ dev_err(ep->dev, "link not up\n");
+ memset(&res, 0x0, sizeof(res));
+ rcar_pcie_set_outbound(window, ep->base, &res, false);
+ return err;
+ }
+
+ if (window >= ep->num_ob_windows) {
+ dev_err(ep->dev, "no free outbound window\n");
+ return -EINVAL;
+ }
+
+ memset(&res, 0x0, sizeof(res));
+ res.start = pci_addr;
+ res.end = pci_addr + size - 1;
+ res.flags = IORESOURCE_MEM;
+
+ rcar_pcie_set_outbound(window, ep->base, &res, false);
+
+ ep->ob_addr[window] = addr;
+
+ return 0;
+}
+
+static void rcar_pcie_ep_unmap_addr(struct pci_epc *epc, u8 fn, phys_addr_t addr)
+{
+ struct rcar_pcie *ep = epc_get_drvdata(epc);
+ struct resource res;
+ int idx;
+
+ for (idx = 0; idx < ep->num_ob_windows; idx++)
+ if (ep->ob_addr[idx] == addr)
+ break;
+
+ if (idx >= ep->num_ob_windows)
+ return;
+
+ memset(&res, 0x0, sizeof(res));
+ rcar_pcie_set_outbound(idx, ep->base, &res, false);
+
+ ep->ob_addr[idx] = 0;
+}
+
+static int rcar_pcie_ep_assert_intx(struct rcar_pcie *ep, u8 fn, u8 intx)
+{
+ u32 val;
+
+ val = rcar_pci_read_reg(ep->base, PCIEMSITXR);
+ if ((val & PCI_MSI_FLAGS_ENABLE)) {
+ dev_err(ep->dev, "MSI is enabled, cannot assert INTx\n");
+ return -EINVAL;
+ }
+
+ val = rcar_pci_read_reg(ep->base, PCICONF(1));
+ if ((val & INTDIS_SHIFT)) {
+ dev_err(ep->dev, "INTx message transmission is disabled\n");
+ return -EINVAL;
+ }
+
+ val = rcar_pci_read_reg(ep->base, PCIEINTXR);
+ if ((val & ASTINTX_SHIFT)) {
+ dev_err(ep->dev, "INTx is already asserted\n");
+ return -EINVAL;
+ }
+
+ val |= ASTINTX_SHIFT;
+ rcar_pci_write_reg(ep->base, val, PCIEINTXR);
+ mdelay(1);
+ val = rcar_pci_read_reg(ep->base, PCIEINTXR);
+ val &= ~ASTINTX_SHIFT;
+ rcar_pci_write_reg(ep->base, val, PCIEINTXR);
+
+ return 0;
+}
+
+static int rcar_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, enum pci_epc_irq_type type,
+ u16 interrupt_num)
+{
+ struct rcar_pcie *ep = epc_get_drvdata(epc);
+
+ switch (type) {
+ case PCI_EPC_IRQ_LEGACY:
+ return rcar_pcie_ep_assert_intx(ep, fn, 0);
+ default:
+ return -EINVAL;
+ }
+}
+
+static int rcar_pcie_ep_start(struct pci_epc *epc)
+{
+ struct rcar_pcie *ep = epc_get_drvdata(epc);
+
+ rcar_pci_write_reg(ep->base, CFINIT, PCIETCTLR);
+
+ return 0;
+}
+
+static void rcar_pcie_ep_stop(struct pci_epc *epc)
+{
+ struct rcar_pcie *ep = epc_get_drvdata(epc);
+
+ rcar_pci_write_reg(ep->base, 0, PCIETCTLR);
+}
+
+static const struct pci_epc_features rcar_pcie_epc_features = {
+ .linkup_notifier = false,
+ .msi_capable = false,
+ .msix_capable = false,
+ /* use 64-bit bars so mark bar1/3/5 as reserved */
+ .reserved_bar = 1 << BAR_1 | 1 << BAR_3 | 1 << BAR_5,
+ .bar_fixed_64bit = (1 << BAR_0) | (1 << BAR_2) | (1 << BAR_4),
+ .bar_fixed_size[0] = 128,
+ .bar_fixed_size[2] = 256,
+ .bar_fixed_size[4] = 256,
+};
+
+static const struct pci_epc_features*
+rcar_pcie_ep_get_features(struct pci_epc *epc, u8 func_no)
+{
+ return &rcar_pcie_epc_features;
+}
+
+static const struct pci_epc_ops rcar_pcie_epc_ops = {
+ .write_header = rcar_pcie_ep_write_header,
+ .set_bar = rcar_pcie_ep_set_bar,
+ .clear_bar = rcar_pcie_ep_clear_bar,
+ .map_addr = rcar_pcie_ep_map_addr,
+ .unmap_addr = rcar_pcie_ep_unmap_addr,
+ .raise_irq = rcar_pcie_ep_raise_irq,
+ .start = rcar_pcie_ep_start,
+ .stop = rcar_pcie_ep_stop,
+ .get_features = rcar_pcie_ep_get_features,
+};
+
+static const struct of_device_id rcar_pcie_ep_of_match[] = {
+ {
+ .compatible = "renesas,rcar-gen3-pcie-ep"
+ },
+ {},
+};
+
+static int rcar_pcie_ep_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct rcar_pcie *pcie;
+ struct pci_epc *epc;
+ int err;
+
+ pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
+ if (!pcie)
+ return -ENOMEM;
+
+ pcie->dev = dev;
+
+ pm_runtime_enable(pcie->dev);
+ err = pm_runtime_get_sync(pcie->dev);
+ if (err < 0) {
+ dev_err(pcie->dev, "pm_runtime_get_sync failed\n");
+ goto err_pm_disable;
+ }
+
+ err = rcar_pcie_ep_get_pdata(pcie, pdev);
+ if (err < 0) {
+ dev_err(dev, "failed to request resources: %d\n", err);
+ goto err_pm_put;
+ }
+
+ pcie->num_ib_windows = MAX_NR_INBOUND_MAPS;
+ pcie->ib_window_map = devm_kcalloc(dev, BITS_TO_LONGS(pcie->num_ib_windows),
+ sizeof(long), GFP_KERNEL);
+ if (!pcie->ib_window_map) {
+ err = -ENOMEM;
+ dev_err(dev, "failed to allocate memory for inbound map\n");
+ goto err_pm_put;
+ }
+
+ pcie->ob_addr = devm_kcalloc(dev, pcie->num_ob_windows, sizeof(*pcie->ob_addr), GFP_KERNEL);
+ if (!pcie->ob_addr) {
+ err = -ENOMEM;
+ dev_err(dev, "failed to allocate memory for outbound memory pointers\n");
+ goto err_pm_put;
+ }
+
+ epc = devm_pci_epc_create(dev, &rcar_pcie_epc_ops);
+ if (IS_ERR(epc)) {
+ dev_err(dev, "failed to create epc device\n");
+ err = PTR_ERR(epc);
+ goto err_pm_put;
+ }
+
+ epc->max_functions = pcie->max_functions;
+ pcie->epc = epc;
+ epc_set_drvdata(epc, pcie);
+
+ err = pci_epc_mem_init(epc, pcie->ob_window, pcie->num_ob_windows);
+ if (err < 0) {
+ dev_err(dev, "failed to initialize the epc memory space\n");
+ goto err_pm_put;
+ }
+
+ rcar_pcie_ep_hw_init(pcie);
+
+ return 0;
+
+err_pm_put:
+ pm_runtime_put(dev);
+
+err_pm_disable:
+ pm_runtime_disable(dev);
+
+ return err;
+}
+
+static struct platform_driver rcar_pcie_ep_driver = {
+ .driver = {
+ .name = "rcar-pcie-ep",
+ .of_match_table = rcar_pcie_ep_of_match,
+ .suppress_bind_attrs = true,
+ },
+ .probe = rcar_pcie_ep_probe,
+};
+builtin_platform_driver(rcar_pcie_ep_driver);
diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/host/pcie-rcar.c
index cbb21d37b539..e8d15163a39d 100644
--- a/drivers/pci/host/pcie-rcar.c
+++ b/drivers/pci/host/pcie-rcar.c
@@ -60,7 +60,10 @@
#define VCCAP(x) (0x010100 + ((x) * 0x4))
/* link layer */
+#define IDSETR0 0x011000
+#define DEVICE_ID_SHFIT 16
#define IDSETR1 0x011004
+#define SUBIDSETR 0x011024
#define TLCTLR 0x011048
#define MACSR 0x011054
#define SPCHGFIN BIT(4)
@@ -101,6 +104,9 @@
#define REXPCAP(x) (EXPCAP(0) + (x))
#define RVCCAP(x) (VCCAP(0) + (x))
+#define INTDIS_SHIFT BIT(10)
+#define ASTINTX_SHIFT BIT(16)
+
#define PCIE_CONF_BUS(b) (((b) & 0xff) << 24)
#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19)
#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16)
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瑞萨开发了专门针对前置摄像头应用的SoC——R-Car V3H，集成了专门针对图像处理的功能单元，它比R-Car V3M在视觉处理方面的性能提高了5倍，并只有0.3瓦的超低功耗，更好的适应自动驾驶的需求。
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Renesas（瑞萨电子）推出驾驶安全辅助系统和车载信息娱乐系统的第三代R-Car SoC芯片，第三代的产品主要包括R-Car H3、R-Car H3N、R-Car M3、R-Car M3N、R-Car D3、R-Car E3、R-Car V3，内核方面使用的是Cortex-A57 CPU、Cortex-A53 CPU和Cortex-R7，主要面向无人驾驶、智能辅助驾驶、车机、仪表和ADAS等应用
【应用】瑞萨R-car H3 处理器芯片助力车载娱乐系统设计
市面上了解到有采用nxp的i.MX 8处理器设计方案做车载娱乐系统的开发，i.MX 8是一款基于基于 Cortex-A72 + Cortex-A53的八核处理器，适用于高级图形、成像、机器视觉、音频、语音、视频应用。其主要内部资源参考如下图1所示。针对如上的设计痛点，推荐选择瑞萨R-car H3处理器做车载娱乐娱乐系统的设计解决方案。
【产品】全新开放式平台，加大对ADAS及自动驾驶的支持
新型R-Car V3M SoC符合ISO26262功能安全标准，为视觉处理提供了低功耗硬件加速功能，还配有内置图像信号处理器。
【经验】R-Car V3M/H接入2片AVT的RX芯片NS2521实现4路摄像头360环视探索的方法
Renesas的R-Car V3M、R-Car V3H的摄像头并口接入瑞发科的AVT接收芯片，实现4路摄像头的图像接入，从而来实现360度环视拼接功能，那么具体是如何对接的呢？本文详细讲解2颗AVT的RX芯片NS2521接入R-Car V3M/H的原理以及具体方法。
R-CAR V3H，V3M指南
描述- 本指南介绍了R-Car V3H和V3M的特点和应用，包括图像信号处理（ISP）、图像渲染单元（IMR）、图像识别引擎（IMP）和卷积神经网络（CNN）等功能。指南还涵盖了摄像头连接、软件支持、评估板和软件包等内容，旨在帮助用户在设计应用前了解R-Car的相关信息。
型号- R-CAR V3M,R-CAR V3H
【经验】R-Car H3的BT656接口摄像头接入设备树修改的方法
R-Car H3是Renesas第三代R-Car汽车自动驾驶平台解决方案，64位ARM架构体系，八核处理器，四个Cortex-A57，四个Cortex-A53，还有一个用于实时处理的双锁步Cortex-R7内核，以及 PowerVR Series6XT GX6650 3D图像加速引擎，频率600MHZ。本文主要介绍R-Car H3的BT656接口摄像头接入设备树修改的方法。
【经验】R-Car H3中如何实现多摄像头的视频数据采集并同时进行H264编码
R-Car系列是瑞萨基于用户越来越高的汽车驾驶体验需求和日渐丰富的产品功能要求，以及汽车产品虚拟化、智能化的行业趋势推出的SoC。本文将以R-Car H3为例，介绍R-Car基于gstreamer实现多摄像头的视频数据采集并同时进行H264编码，该功能主要应用于自动驾驶域控制器，可实现视频数据的采集、编码和实时分发。
【经验】基于R-Car H3特殊的PCB叠层方案，车载域控制器中R-Car H3与LPDDR4之间的布线方法
瑞萨R-Car H3处理器（SOC）是汽车域控制器专用SOC，它拥有1384个PIN，功能多、系统复杂，PIN密度很大而PIN间距很小，这些特点要求以它为载体的车载域控制器的PCB叠构是很特别的，本文中，笔者将以其特殊的PCB叠层方案为基础，分享车载域控制器中R-Car H3与LPDDR4之间的布线应用方案。
【经验】R-Car H3上实时核移植freertos系统bootloader的关键点
R-Car H3是Renesas第三代R-Car汽车自动驾驶平台解决方案，64位ARM架构体系，八核处理器，四个Cortex-A57，四个Cortex-A53，还有一个用于实时处理的双锁步Cortex-R7内核，以及 PowerVR Series6XT GX6650 3D图像加速引擎，频率600MHZ。本文主要介绍R-Car H3 上实时核移植freertos系统，bootloader的关键点。
【应用】基于R-Car V3M的智能摄像头解决方案，提供高效图像识别引擎与功能安全特性
Renesas推出的R-Car V3M智能摄像头解决方案，这款解决方案提供了高效图像识别引擎、功能安全特性和高水平的集成，从而实现前置摄像头应用，全景影像，和激光雷达系统或符合新车评价规程 (NCAP) 评估标准的激光探测与测距系统。
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