The totem-pole PFC stage comes of age with SiC FETs

The totem poles found in the US pacific northwest have a range of functions, from decorative to memorial, some signing a welcome, some an exercise in public shaming or ridicule. I’m not sure which was in the engineer’s mind when they decided to apply the name to a stack of two transistors driven in a complementary way in TTL logic, but the term is certainly now a welcome addition to the power world, in the form of the ‘totem-pole’ power factor correction stage. The connection with monumental carvings is still a bit tenuous but the similarity with a TTL output stage is still there – two sets of stacked switches, driven alternately, one leg at AC line frequency and one leg at high frequency.

The point of the arrangement is that it can be deconstructed to be equivalent to a full bridge AC rectifier followed by a power factor correcting boost circuit, but practically with fewer elements in line with the power flow, giving lower losses. Only two line-AC rectifier diodes are needed in the totem-pole circuit and even these could be replaced by synchronous rectifying MOSFETs for even lower losses.  The scale of it is that a bridge rectifier can contribute to close to 2% loss in efficiency at low line in an AC/DC converter, and when target efficiency for a power supply from end to end can be 96% to meet 80+ Titanium standards, 2% is well worth eliminating.

How it works

In the circuit, for one polarity of line AC, one switch, say Q1, is set to conduct and Q2 to block. Power is then fed in that polarity to Q3 and Q4 which form a classic PFC boost converter with Q3 as the switch and Q4 operating as a synchronous rectifier to produce around 400V DC from standard mains. On the other AC line polarity, Q2 conducts, Q1 blocks and the opposite polarity of half sine is routed to the boost converter, but now Q4 is the switch and Q3 configured as a synchronous rectifier producing the same high-voltage DC rail. With synchronous switches as diodes, the circuit has conduction losses limited only by semiconductor on-resistances and the inductor and connection ohmic resistances. 

As switch technology has progressed, MOSFETs for example can now have RDS(on) values that would seem to make them ideal in the circuit up to relatively high power. There is a problem though, with silicon MOSFETs, dynamic losses can be so high as to make the circuit unworkable. The main problem is the power dissipated due to the recovery of the body diode of the MOSFETs when operating as boost synchronous rectifiers. There is always a ‘dead time’ between the MOSFET channel being actively driven off and on, to avoid cross conduction, and during this time the integral body diode conducts by ‘commutation’, storing the offending charge. The effect only occurs in the ‘continuous conduction’ mode where inductor current never falls to zero in each switching cycle, but this is the preferred mode at higher powers to keep peak and rms current in the switch and inductor within practical values for low conduction losses.

Wide band-gap switches enable a viable solution

The totem-pole PFC stage therefore languished as a tantalizing topology from its first proposal until semiconductor technology caught up, in the form of wide band-gap semiconductors. Silicon carbide MOSFETs have much lower body diode reverse recovery charge than their silicon counterparts and gallium nitride HEMT cells have none at all, so the topology’s day has come. We can now realistically talk about 99%-plus efficiency in an AC/DC front end, but the practical implementation still has some difficulties with very specific gate drive conditions necessary for both SiC MOSFETs and GaN to extract the last decimal point of efficiency and maintain reliability.

The gate drive issue is solved by designing with SiC FETs from UnitedSiC, a cascode combination of a SiC JFET and a silicon MOSFET. The gate now can be driven at ‘normal’ MOSFET or IGBT levels with a large margin of safety to the absolute maximum +/- values, with a stable threshold level when driving the device fully on, largely independent of time and temperature. But wait, there’s more – the SiC FET has much lower on-resistance for the same die area as SiC MOSFETs and GaN  transistors at the same voltage class, so die per wafer is improved and conversely, for the same on-resistance, die area can be smaller, giving lower device capacitances and consequently lower switching loss. The net result is lower overall losses, an easy gate drive, and the reassurance that reliability isn’t compromised with a high energy avalanche rating which is absent in GaN devices.

The word totem comes from the Algonquian ‘odoodem’ meaning ‘kinship group’ perhaps a nice reference to the happy marriage of an elegant topology and near-ideal SiC FET switches.